The present embodiment relates to a semiconductor device and in particular relates to a semiconductor memory having a word driver circuit in which leakage current is suppressed.
In recent years there is a tendency for dynamic RAM (DRAM) to be used as large-capacity memory of battery-driven electronic equipment such as cellular phone. In particular, the demand for pseudo-SRAM has increased since pseudo-SRAM is a type of DRAM a refresh command can be generated internally and does not need to be supplied from outside, but the memory cells are DRAM.
In DRAM having such applications, reduction of the current consumption during standby is required in order to prolong the standby time of the cellular phone that can be achieved with the battery. Current consumption during standby includes the AC current for refresh operation, the DC current needed for operation of the power source circuit, and the sub-threshold current and the gate induced drain leakage current (GIDL) of the transistors.
In particular, the internal power source of recent DRAMs includes a boosted voltage (Vpp) that is boosted from the external power source (Vdd), and a negative power source Vnwl (nwl: negative word line) that is lower than ground (Vss). The boosted voltage Vpp is used as word line selection potential: the restore potential of the cell can be raised by applying high boosted voltage Vpp to the gate of the cell transistor. In contrast, the negative power source Vnwl is utilized as the word line non-selection potential and makes it possible to reduce the sub-threshold leakage current of the cell transistor.
On the other hand, the drive capacity of the word line is reduced by using a segmented word line structure as the word line structure of the DRAM. With a segmented word line structure, a main word line is provided with a plurality of sub-word lines, the main word line being selected by a main word decoder, and, in addition, sub-word lines being selected by a sub-word decoder. Also, a sub-word driver circuit is used to drive a single sub-word line based on logic of a selected main word line and a selected sub-word decoding signal.
An example of a segmented word line layout having such main word lines and sub-word lines is disclosed for example in Laid-open Japanese Patent Application No. H10-312682 and in Laid-open Japanese Patent Application No. H11-86543. Laid-open Japanese Patent Application No. H10-312682 states that the area of a sub-word driver can be reduced by constituting the sub-word driver using one PMOS and two NMOS transistors. Also, Laid-open Japanese Patent Application No. H11-86543 describes a sub-word driver circuit arranged to be capable of driving a sub-word line with boosted potential and negative potential.
In a segmented word line construction, the sub-word driver circuits comprise CMOS circuits comprising three transistors. Specifically, the selected main word line is driven to L level, and the selected sub-word decoding signal is driven to H level, and therefore the sub-word line is driven to H level (selection level) by a PMOS transistor of the sub-word driver circuit. Also, the non-selected main word lines are driven to H level, and the sub-word lines are driven to L level (non-selected level) by an NMOS transistor of the sub-word driver circuit. The sub-word line can be driven to L level (non-selected level) by the second NMOS transistor by making the sub-word decoding signal L level and making the inverted sub-word decoding signal H level, even if the main word line is L level (selection level).
As described above, by using boosted potential Vpp for the word line H level and using negative potential Vnwl for the word line L level, excess voltage is applied to the PMOS and NMOS transistors of the word driver circuit, causing the GIDL current on standby to increase. In particular, when the transistors are made of extremely small size in order to achieve high RAM capacity, the increase in GIDL current reaches a level that cannot be neglected.
The GIDL current depends on the gate voltage of the transistor and is the current that flows between the substrate and source or drain in the vicinity directly below the gate electrode. For example, in the case of a PMOS transistor, when negative potential Vnwl is applied to the source or drain and boosted potential Vpp is applied to the substrate and gate, the GIDL current is increased. Likewise in the case of an NMOS transistor, the GIDL current is increased when boosted potential Vpp is applied to the source or drain and negative potential Vnwl is applied to the substrate and gate.
When the GIDL current increases, it is necessary to further actuate the pumping action of the pumping circuits that generate the power sources Vpp and Vnwl of the word driver and this tends to result in increased current consumption during standby. In other words, increase in the GIDL current makes it necessary for the pumping circuits to pump more charge. Regarding the efficiency of these pumping circuits, the current supplied to the boosted potential Vpp is only of the order about 25% of the current of the external power source Vdd, and the current supplied to the negative potential Vnwl is only about 80% of the current of the external power source Vdd, so, combining these two, the efficiency of these pumping circuits is only about 20%. Consequently, the effective efficiency of pumping current generation by the pumping circuits is further lowered by the current between Vpp and Vnwl produced by the GIDL current, thereby tending to increase the current of the external power source Vdd to an extent that cannot be neglected.